There are some conventional semiconductor devices in which two wiring layers in an upper layer are connected via an wiring layer in a lower layer and contact plugs (refer to Patent Documents 1 and 2, for example). Referring to Patent Document 1, a lower electrode 130c connected to a contact plug is electrically connected to an interconnect 123c formed of a polysilicon film via an opening 127c, and is then electrically connected to an interconnect 133c via a contact plug 130d (refer to FIG. 20). Referring to Patent Document 2, an interconnect 206a is electrically connected to an interconnect 206b via a contact plug 204a, a high-resistance element layer 211, and a contact plug 204b (refer to FIG. 21).
[Patent Document 1] JP Patent Kokai Publication No. JP-P2000-164812A
[Patent Document 2] JP Patent Kokai Publication No. JP-P2003-243522A
[Patent Document 3] JP Patent Kokai Publication No. JP-A-8-181205
[Patent Document 4] JP Patent Kokai Publication No. JP-P2002-353328A